Timer of PIC16F873

Timer 0

The specification of timer0 is same as PIC16F84A. It has following features.

		8 bits timer/counter TMR0 ( It can count up to 255 )
		Readable and Writable counter
		8 bits software programmable prescaler ( Shared with watchdog timer. It can be used in either)
		Selectable internal clock or external clock
		Interrupt on overflow from FFh to 00h
		Edge select for external clock ( Rising edge or falling edge )

As for the specification, refer to the specification of the timer (TMR0).

Timer 1

The timer1 module is a 16 bits timer/counter consisting of two 8 bits registers( TMR1H and TMR1L ). Also it has prescaler. It can be selected four values.
The overflow interruption can be enabled/disabled by setting/clearing TMR1 interrupt enable bit TMR1IE of PIE register. The interruption occurs when the counter rolls over to 0000h from FFFFh.

There are a timer mode and a counter mode in timer1. The operating mode is determined by the clock select bit ( TMR1CS bit of T1CON register ). In case of TMR1CS is cleared, it works as Timer, and in case of TMR1CS is set, it works as Counter.



Timer mode
In timer mode, Timer1 increments every instruction cycle (FOSC/4). Timer1 can be enable/disable by setting/clearing control bit ( TMR1ON bit of T1CON register ). Also, timer1 has an internal reset input. This reset can be generated by either of two CCP modules.

When the timer1 oscillator is enabled by setting T1OSCEN bit of T1CON register. In the case, it connects a crystal oscillator with Pin 11 and pin 12. The oscillation frequency is possible to 200KHz. These pins combine the input/output pin of RC0 and RC1. However, the feature as the input/output pin is ignored. The setting of TRISC register is ignored too.

Counter mode
In counter mode, Timer1 increments on every rising edge of clock input.
When T1OSCEN bit of T1CON register is cleared, Timer1 increments on every rising edge of clock input on pin RC0/T1OSO/T1CKI( pin 11 ).
When T1OSCEN bit of T1CON register is set, Timer1 increments on every rising edge of clock input on pin RC1/T1OSI/CCP2( pin 12 ).
After Timer1 is enabled in counter mode, the module must first have a falling edge before the counter begins to increment. When started from the L level, the first rising edge isn't counted.
If T1SYNC bit of T1CON register is cleared, the external clock input is synchronized with internal phase clocks. The synchronization is done after the prescaler stage.

In Capture and Compare mode of CCP, timer1 is used.
In case of the asynchronous counter mode, the counter can not be used for the capture or compare feature.
As for the operation of the CCP, refer to CCP feature of PIC16F873.

Timer 2

Timer2 is an 8 bits timer with a prescaler and a postscaler and it has an 8 bits period register PR2 The input clock (Fosc/4) has a prescale option of 1:1, 1:4 or 1:16 selected by T2CKPS1 and T2CKPS0 bits of T2CON register. The match output of TMR2 goes through a 4 bits postscaler which gives a 1:1 to 1:16 scaling inclusive.

Timer2 increments from 00h until it matches PR2 and then reset to 00h on the next increment cycle. Then timer2 repeats incrementation from 00h to the value of PR2. The PR2 register is initialized to FFh upon reset. The match output of TMR2 goes through a postscaler to generate a TMR2 interruption ( latched in flag bit TMR2IF of PIR register ). Timer2 can be shut off by clearing TMR2ON bit of T2CON register to minimize power consumption.

Timer 2 is used for the PWM feature of CCP mainly. It is used to control the period of the continuation pulse.
As for the operation of the CCP, refer to CCP feature of PIC16F873.