CP1,CP0 : Flash Program Memory Code
Protection Bits.
 All of the CP1:CP0 pairs have to be given the
same value to enable the code protection scheme listed. |
 |
11 |
: |
Code protection off |
| 10 |
: |
0F00h to 0FFFh code protected |
| 01 |
: |
0800h to 0FFFh code protected |
| 00 |
: |
0000h to 0FFFh code
protected | |
|
|
|
DEBUG : In-Circuit Debugger
Mode |
|
1 |
: |
In-Circuit Debugger disabled, RB6 and RB7 are
general purpose I/O pins. |
| 0 |
: |
In-Circuit Debugger enabled, RB6 and RB7 are
dedicated to the debugger. | |
|
|
|
WRT : Flash Program Memory Write
Enable |
|
1 |
: |
Unprotected program memory may be written to
by EECON control |
| 0 |
: |
Unprotected program memory may not be written
to by EECON control | |
|
|
|
CPD : Data EEPROM memory Code
Protection |
|
1 |
: |
Code protection off |
| 0 |
: |
Data EEPROM memory code
protected | |
|
|
|
LVP : Low Voltage In-Circuit Serial
Programming Enable bit |
|
1 |
: |
RB3/PGM pin has PGM function, low voltage
programming enabled
The high voltage
programming mode is always available, regardless of the state
of the LVP bit. |
| 0 |
: |
RB3 is digital I/O, High Voltage on MCLR must
be used for programming | |
|
|
|
BODEN : Brown-out Reset Enable
bit |
|
1 |
: |
BOR enabled |
| 0 |
: |
BOR disabled | |
|
|
|
PWRTE : Power-up Timer Enable
bit |
|
1 |
: |
PWRT disabled |
| 0 |
: |
PWRT enabled | |
|
|
|
WDTE : Watchdog Timer Enable
bit |
|
1 |
: |
WDT enabled |
| 0 |
: |
WDT disabled | |
|
|
|
FOSC1,FOSC0 : Oscillator Selection
bits |
|
11 |
: |
RC : Resistor/Capacitor oscillator ( Less
than 1MHz ) |
| 10 |
: |
HS : High Speed Crystal/Resonator oscillator
( 4MHz to 20MHz ) |
| 01 |
: |
XT : Crystal/Resonator oscillator ( Less than
4MHz ) |
| 00 |
: |
LP : Low Power Crystal oscillator ( Less than
200KHz
) | |
Pic in Greek
